january 2006 FDC658AP single p-channel logic level powertrench ? mosfet ?2006 fairchild semiconductor corporation FDC658AP rev. b (w) www.fairchildsemi.com 1 FDC658AP single p-cha nnel logic level powertrench ? mosfet -30v, -4a, 50m ? general description this p-channel logic level mosfet is produced using fairchild's advanced powertrench process. it has been optimized for battery power management applications. applications ? battery management ? load switch ? battery protection ? dc/dc conversion features ? max r ds(on) = 50 m ? @ v gs = -10 v, i d = -4a ? max r ds(on) = 75 m ? @ v gs = -4.5 v, i d = -3.4a ? low gate charge ? high performance trench technology for extremely low r ds(on) ? rohs compliant absolute maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain-source voltage -30 v v gs gate-source voltage 25 v i d drain current - continuous -4 a -20 p d maximum power dissipation 1.6 w 0.8 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction-to-ambient 78 c/w r jc thermal resistance, junction-to-case 30 c/w device marking device reel size tape width quantity .58a FDC658AP 7inch 8mm 3000 units pin 1 supersot tm -6 s d d g d d 5 1 6 2 3 4 (note 1a) (note 1a) (note 1b) (note 1) (note 1a) - pulsed
FDC658AP single p-channel logic level powertrench ? mosfet FDC658AP rev. b (w) www.fairchildsemi.com 2 electrical characteristics t j = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain-source breakdown voltage i d = -250 p a, v gs = 0v -30 v ' bv dss ' t j breakdown voltage temperature coefficient i d = -250 p a, referenced to 25 c -22 mv/ c i dss zero gate voltage drain current v gs = 0v, v ds = -24v -1 p a i gss gate-body leakage v gs = r 25v, v ds = 0v r 100 na on characteristics v gs(th) gate threshold voltage v ds = v gs , i d = -250 p a -1 -1.8 -3 v ' v gs(th) ' t j gate threshold voltage temperature coefficient i d = -250 p a, referenced to 25 c 4 mv/ c r ds(on) static drain-source on-resistance i d = -4a, v gs = -10v 44 50 m : i d = -3.4a, v gs = -4.5v 67 75 i d = -4a, v gs = -10v, t j = 125 c 60 70 i d(on) on-state drain current v gs = -10v, v ds = -5v -20 a g fs forward transconductance i d = -4a, v ds = -5v 8.4 s (note 2) dynamic characteristics c iss input capacitance v ds = -15v, v gs = 0v, f = 1mhz 470 pf c oss output capacitance 126 pf c rss reverse transfer capacitance 61 pf switching characteristics (note 2) t d(on) turn-on delay time v dd = -15v, i d = -1a v gs = -10v, r gen = 6 : 7 14 ns t r turn-on rise time 12 22 ns t d(off) turn-off delay time 16 29 ns t f turn-off fall time 6 12 ns q g total gate charge v ds = -15v, i d = -4a, v gs = -5v 6 8.1 nc q gs gate-source charge 2.1 nc q gd gate-drain charge 2 nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -1.3 a v sd drain-source diode forward voltage v gs = 0v, i s = -1.3 a (note 2) -0.77 -1.2 v notes: 1: r t ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the drain pins. r t jc is guaranteed by design while r t ca is determined by the user's board design. scale 1: 1 on letter size paper 2: pulse test: pulse width < 300 p s, duty cycle < 2.0% a) 78 o c/w when mounted on a 1 in 2 pad of 2 oz copper b) 156 o c/w whe mounted on a minimum pad of 2 oz copper
FDC658AP single p-channel logic level powertrench ? mosfet FDC658AP rev. b (w) www.fairchildsemi.com 3 typical characteristics figure 1. 0 5 10 15 20 01234 5 -v ds , drain to source voltage (v) -i d , drain current (a) v gs = -10v -3.5v -3.0v -4.5v -4.0v -5.0v -6.0v on-region characteristics figure 2. 0.8 1 1.2 1.4 1.6 1.8 2 0 4 8 12 16 2 0 -i d , drain current (a) normalized drain to source on-resistance v gs = -4.5v -6.0v -5.0v -8.0v -7.0v -10v normalized on-resistance vs drain current and gate voltage figure 3. 0.6 0.8 1 1.2 1.4 1.6 -50-25 0 25507510012515 0 t j , junction temperature ( o c) normalized drain to source on-resistance i d = -4.0a v gs = -10 v normalized on-resistance vs junction temperature figure 4. 0.02 0.06 0.1 0.14 0.18 0.22 24681 0 -v gs , gate to source voltage (v) r ds(on) , drain to source on resistance (ohm) i d = -2.0a t j = 125 o c t j = 25 o c on-resistance vs gate to source voltage figure 5. transfer characteristics 0 3 6 9 12 15 12345 -v gs , gate to source voltage (v) -i d , drain current (a) t j = -55 o c 25 o c 125 o c v ds = -5v figure 6. 0.0001 0.001 0.01 0.1 1 10 00.20.40.60.811. 2 -v sd , body diode forward voltage (v) -i s , reverse drain current (a) v gs = 0v t j = 125 o c 25 o c -55 o c source to drain diode forward voltage vs source current
FDC658AP single p-channel logic level powertrench ? mosfet FDC658AP rev. b (w) www.fairchildsemi.com 4 figure 7. 0 2 4 6 8 10 024681 0 q g , gate charge (nc) -v gs , gate-source voltage (v) i d = -4a v ds = -5v -10v -15v gate charge characteristics figure 8. 0 150 300 450 600 0 6 12 18 24 3 0 -v ds , drain to source voltage (v) capacitance (pf) c iss c oss c rss f = 1 mhz v gs = 0 v capacitance vs drain to source voltage figure 9. 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain to source voltage (v) -i d , drain current (a) dc 1s 100ms 100us r ds(on) limit v gs = -10v single pulse r ja = 156 o c/w t a = 25 o c 10ms 1ms forward bias safe operating area figure 10. 0 2 4 6 8 10 0.01 0.1 1 10 100 t, pulse width (s) p(pk), peak transient power (w) single pulse r ja = 156c/w t a = 25c single pulse maximum power dissipation figure 11. 0.001 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, rectangular pulse duration r(t), normalized effective transient thermal resistance r ja (t) = r(t) + r ja r ja = 156 o c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p (p k ) t 1 t 2 single puls e 0.01 0.02 0.05 0.1 0.2 d = 0. 5 transient thermal response curve thermal characterization performed usi ng the conditions described in note 1b. transient thermal response will change depending on the circuit board design. typical characteristics
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